This invention pertains generally to semiconductors and more particularly to complementary semiconductor structures and method of fabricating the same.
Semiconductor devices such as CMOS integrated circuits commonly contain parasitic PNPN structures which can give rise to an undesired SCR action commonly known as "latch-up", wherein the device is turned on by forward biasing of one of the junctions in the PNPN structure. The device remains "on" even after the signal which produced the forward biasing is removed, and this can lead to destruction of the device or metal by excessive current flow.
Heretofore, there have been attempts to eliminate latch-up in such devices by techniques such as turning on power supplies in special sequences, using external components, or avoiding transients. However, there are many applications in which these techniques cannot be employed successfully.
There have also been attempts to eliminate latch-up through fabrication techniques such as the use of dielectric insulation to eliminate parasitic transistors in a CMOS device. Other such techniques have included the use of a sapphire substrate and the reduction of current gain by decreasing minority carrier lifetime in the base by techniques such as gold doping, exposing the CMOS structure to X-ray and gamma ray radiation, and the use of a very deep base with a low current gain and a high minority base transit time. These techniques are subject to a number of problems, including excessive junction leakage, failure to completely eliminate latch-up, low device yield, limited throughput, and high manufacturing cost.